Toshiba has enhanced its NAND flash portfolio with the introduction of next-generation 24-nanometer (nm) generation "SmartNAND," which integrate robust error management into the NAND package.

The new chips will be available in capacities of up to 64GB and will support simplified host-side design and application of advanced NAND process generation in consumer applications, including digital audio players, tablet PCs, information equipment, digital TVs, set-top boxes and other applications that require high-density, non-volatile memory.

Samples of the new SmartNAND line-up will be available from middle of April, and mass production will start in the second quarter of CY2011 (April to June), Toshiba said.



The SmartNAND series packages integrate 24nm process NAND flash technology with a control chip supporting error correction code (ECC). The five devices in the latest line-up range from 4 to 64 gigabyte (GB) capacities, and are expressly designed to remove the burden of ECC from the host processor while minimizing protocol changes. The SmartNAND portfolio is targeted for portable media players, tablet PCs and other consumer digital products etc.

The new 24nm product line-up will replace current 32nm generation devices, and its advanced process combined with faster controller and internal interface will realize faster read and write speeds and enhance overall performance.

The integrated error correction (ECC) and the 24nm process generation result to a 1.9x faster read speed and 1.5x faster write speed than current line-up, Toshiba said.

SmartNAND also supports a range of read and write speeds, optimized to suit design objectives, and four read modes and two write modes will be offered.

The new products utilize the long established raw NAND interface, and include new features that are optimized for high-capacity and high-performance applications.

Specifications

Interface: Standard NAND flash memory interface
Page Size: 8K Byte
Voltage: Vcc=2.7~3.6V

Read & Write Mode:
4 Type Read Mode, 2 Type Write Mode
Power Save Mode is applicable to all functions

Normal Mode & Reliable Mode:
Normal Mode; MLC(2bit/Cell)
In reliable mode, it operates as pseudo SLC, and the host side can set the area in block or chip basis for normal mode or reliable mode.

Package:
48 pin TSOP(12mm x 20mm x 1.2mm)
52 land LGA (14mm x 18mm x 1.0mm)