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Thursday, February 10, 2011
Elpida and Rexchip Achieve 1-Gigabit DDR3 SDRAM Prototype


Elpida Memory and Rexchip Electronics today announced the successful joint pilot production of 1-gigabit DDR3 SDRAMs featuring 4F2 memory cell architecture. The pilot run was handled at Rexchip's R&D Center.

Rexchip's R&D Center, which began R&D operations in 2010, has been working with Elpida to develop 4F2 cells in DRAMs. The two companies have now succeeded to make a prototype 1-gigabit DDR3 SDRAM with 4F2 cells using a 65nm design rule.

The 4F2 memory cell developed by Elpida and Rexchip forms the bitlines and wordlines into the silicon and uses a vertical transistor to achieve a 2F x 2F memory cell size (F is the minimum feature size). Compared with 6F2 memory cells, the 4F2 cell size is 30% smaller while chip size and chip output are roughly the same as Elpida's DRAMs in the 50nm process node class. Also, the excellent data retention characteristics and the high-performance vertical transistor structure of 4F2 cells are likely to become the fundamental technology for next-generation DRAMs. In addition, 4F2 architecture has the potential to meet requirements for low power mobile DRAMs.

Yukio Sakamoto, president and CEO of Elpida, said: "This successful pilot production of 4F2 memory cells was made possible by powerful basic technology that will be critical to the development of next-generation DRAMs using 20nm and beyond process node technologies. Elpida and Rexchip moving ahead quickly to jointly develop this technology was the key to our success and now positions us as future technology leaders in the DRAM industry."

The development of the 4F2 memory cell by the two companies was achieved through close cooperation between Japanese and Taiwanese engineers.


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