Panasonic has developed an inertial sensor signal processing IC chip
measuring less than 2mm on each side, realizing the smallest size in
the world.
The company has achieved this technology by developing 1.8V 110nm
BiCMOS with the industry's minimum design rule, allowing the surface
area of the high-precision analog circuits to be halved. Mass
production of the IC chips has already begun this month, Panasonic
said. This newly developed technology will soon be deployed in signal
processing ICs for various sensors.
Panasonic's inertial sensor signal processing IC chips help reduce
the size and enhance the functions of inertial sensor modules to be
used in various different products, including mobile products and
game machines.
In order to miniaturize inertial sensor modules, the great challenge
has involved the size of the sensor signal processing ICs which,
though just a few square millimeters, occupy a large space within the
module. Sensor signal processing ICs amplify faint signals outputted
from a sensor and convert them to electrical signals depending on the
inertial force. Since approximately 80% of the area of such an IC
chip is occupied by high-precision analog circuits, it had been
considered difficult to reduce the area of the IC through fine
process formation.
The sensors themselves have also been miniaturized, causing the level
of sensor signals to be reduced. This phenomenon necessitated a
reduction in low-frequency noise generated in the first-stage
amplifier circuit, which amplifies the sensor signals. However, the
noise reduction would then result in an increase in area with
conventional CMOS analog circuits. Furthermore, recent industry
demands have focused on the high functionality of sensor modules,
such as built-in AD converters and multi-axes, which again results in
an increase in area for the sensor signal processing ICs.
These issues have now been resolved by Panasonic's inertial sensor
signal processing ICs, which have the following features:
1. The world's smallest chip size: reduced to 40% of the
conventional chip area (300nm process)
2. Low-frequency noise (1/f noise) generated in the first-stage
amplifier: reduced to 1/10 of that of conventional amplifiers -
allowing the sensor sensitivity to be improved and therefore
compensating for the reduction in output signal caused by the
miniaturization of the sensor.
3. Built-in AD converters: easy connection to the latter-stage
LSIs and more flexible design, using digital rather than analog
output signals.
Panasonic has succeeded in the development of these inertial sensor
signal processing ICs by utilizing the following technologies:
1. BiCMOS with the industry's smallest 110nm design rule;
developed by means of a 1.8V CMOS core transistor process.
2. The first-stage amplifier has been designed using the
industry's smallest bi-polar transistors, using DTIs molded in a
110nm process. The advantage of bi-polar transistors is that
low-frequency noise generated by the transistors themselves is
approximately 1/100 the level generated by the conventional CMOS
analog circuits.
3. Newly developed, small-sized delta-sigma AD converters
operating at 1.8V, with a signal power/noise power (S/N) ratio
reaching 99dB.