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 Home > News > General Computing > Hynix, ...
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Wednesday, December 08, 2010
Hynix, IBM And Samsung Talk About Latest STT RAM Developments at IEDM


During the International Electron Device Meeting (IEDM) in Sans Francisco this week, IBM, Samsung and the Hynix presented papers on Spin torque MRAM, or STT RAM.

Spin torque MRAM, or STT RAM is a next-generation MRAM technology. The nonvolatile memory technology is said to combine high speed operations with low power.

Samsung Electronics has tested STT-MRAM for the replacement of DRAM and NOR.

"For competition with DRAM, STT-MRAM unit cell size should be reduced to 6 ~ 8F2 and switching current density is required to be less than 1 MA/cm2. Here, we report that the cell characteristics of on-axis STT-MRAM with 6 ~ 8F2 are similar to those of the off-axis STT-MRAM with 12 ~ 16F2. In addition, we suggest a novel MTJ with the operation current density of 0.8 MA/cm2. These results open a way to scale STT-MRAM down to sub-30 nm node using present technology. By further material engineering of ferromagnetic electrode and MTJ structure design, the usage of present technology could be extended down to sub-20 nm node," Samsung said.

Hynix Semiconductor Inc. and Grandis Inc. are taking another approach.

"To compete with existing memories, the emerging memory should have a comparable unit cell dimension. We demonstrated the 64Mbit STT-RAM technology with a 14F2 cell at the 54nm node. The compact cell can provide a large enough current drivability and also a stable MTJ performance," the companies said.

Hynix also talked about the challenges in scaling semiconductor memory technologies. On DRAM and NAND Flash the technology scaling-down is at risk below 20nm, the company said. Hynix introduced some recent progress on overcoming scaling challenges of current and new memory technologies and also reviewed some of the possible technology replacements are reviewed.

IBM-MagIC MRAM Alliance-the joint MRAM venture between IBM and TDK Corp.-disclosed details of its technology-a perpendicular spin torque MRAM. In the paper entitled "Switching Distributions and Write Reliability of Perpendicular Spin Torque MRAM," the companies reported "data from 4-kbit spin torque MRAM arrays using tunnel junctions (TJs) with magnetization perpendicular to the wafer plane.

"We show for the first time the switching distribution of perpendicular spin torque junctions," according to the paper. "The percentage switching voltage width, alpha(Vc)/ = 4.4 percent, is sufficient to yield a 64-Mb chip," according to the paper.

"Furthermore we report switching probability curves down to error probabilities of 5x10-9 per pulse which do not show the anomalous switching seen in previous studies of in-plane magnetized bits."


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