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Friday, November 26, 2010
New Processor Technologies On Stage of ISSCC 2011

IBM, Intel and AMD will take the stage at ISSCC 2011 conference and will talk about their efforts to develop high-performance, low-power processors, including a 5.2Ghz microprocessor chip, a 10-core Xeon and a dual-core Bulldozer processor running at 3.5+ GHz.

IBM will present a microprocessor chip for the IBM zEnterprise 196 system, which contains 4 processor cores running at 5.2GHz, and includes an on-chip high-speed 24MB shared DRAM L3 cache. To meet this high-frequency design objective, many challenges were met, including significant timing, power and noise problems which had to be resolved.

Intel will talk about a monolithic 10-core Xeon Processor designed in a 32nm 9M process with a shared L3 cache. Low power modes are introduced to cut idle power compared to the previous generation processor. A 2nd order CTLE and temperature compensation are implemented in the I/O receiver to enable link survivability even with low RX margins. Intel's core- and cache-recovery techniques maximize yield.

Intel will also describe a 32nm Itanium processor for mission-critical servers. The Itanium processor implemented in 32nm CMOS has 9 layers of Cu and contains 3.1 billion transistors. The processor's die measures 18.2?29.9mm2 and has 8 multi-threaded cores, a ring-based system interface and combined cache on the die is 50MB. High speed links allow for peak processor-toprocessor bandwidth of up to 128GB/s and memory bandwidth of up to 45GB/s, Intel says.

AMD will present design Solutions for its Bulldozer 32nm Soi 2-core processor. The Bulldozer 2-core CPU module contains 213M transistors in an 11-metal layer 32nm high-k metalgate SOI CMOS process and is designed to operate from 0.8 to 1.3V. This micro-architecture improves performance and frequency while reducing area and power over a previous AMD x86-64 CPU in the same process. The design reduces the number of gates/cycle relative to prior designs, achieving 3.5GHz+ operation in an area (including 2MB L2 cache) of 30.9mm2, AMD says.

In addition, AMD will present a 40-entry unified out-of-order scheduler and integer execution unit for the aMd Bulldozer x86-64 core. The 40-instruction out-of-order scheduler issues four operations per cycle and supports single-cycle operation wakeup. The integer execution unit supports single-cycle bypass between four functional units. AMD implemented critical paths without exotic circuit techniques or heavy reliance on full-custom design. AMD's architectural choices also minimize power consumption.

The 2011 IEEE International Solid-State Circuits Conference will be held on February 20-24, 2011, in the San Francisco, CA.

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