Tuesday, February 21, 2017
Search
  
Submit your own News for
inclusion in our Site.
Click here...
Breaking News
Intel Optane Memory Products Will Run Only On Systems With 7th Generation Intel Processors
Google, Bing Agree to Help U.K. Fight Pirate Sites
Researchers Create Printed ICs that Can Stretch
SK Telecom to Unveil Live Streaming Platform for 360 VR at MWC 2017
Samsung Develops 5G Mobile Communication Chip
LG Display Confirms LCD Supply Deal With Rival Samsung
LG's G6 Smartphone To Feature A Wide-angle Dual Camera
New Samsung Galaxy Tab S Series To Include Windows Version
Active Discussions
Which of these DVD media are the best, most durable?
How to back up a PS2 DL game
Copy a protected DVD?
roxio issues with xp pro
Help make DVDInfoPro better with dvdinfomantis!!!
menu making
Optiarc AD-7260S review
cdrw trouble
 Home > News > General Computing > TSMC Ne...
Last 7 Days News : SU MO TU WE TH FR SA All News

Tuesday, June 15, 2010
TSMC New Standard Cell Slim Library Reduces Logic Area


Taiwan Semiconductor Manufacturing Company today introduced the first Slim Library that reduces system-on-chip (SoC) routed logic block area by 15 percent compared to blocks routed through current standard cell libraries.

The library targets TSMC's 65nm LP process technology and fits existing implementation flows for easy adoption. Designers can use the new Slim Library in existing or new designs without change to design tools and implementation methodologies.

Slim Library is the result of the AreaTrim design and process co-optimization program between the TSMC and Tela Innovations. The library is based on Tela's patented layout style and TSMC's process optimization. The two companies demonstrated the 15% area improvement through synthesis and timing-driven place and route implementations on multiple versions of widely used microprocessor cores.

The new library's layout style draws a lithography-optimized pattern with uniform density through unidirectional poly on a fixed pitch and improved manufacturing process control to reduce area. As a result, Slim Library achieves gate densities of up to 1 million gates per square millimeter.

Slim Library is re-designed into 8 tracks from the traditional 9-track configuration, yet provides equivalent performance and power. The library includes Multiple Vt options and power management cells along with full set of characterization corners.

The new 65LP Slim Library is available now in limited release through the TSMC Online customer design portal (http://online.tsmc.com/online) or by contacting local TSMC account management or support representatives. General release is targeted for the first quarter of 2011.


Previous
Next
European Research Project Aims for Greener Electronics        All News        Khronos Releases OpenCL 1.1 Specification
European Research Project Aims for Greener Electronics     General Computing News      Toshiba develops Silicon Nanowire Transistor for 16nm Generation and Beyond

Get RSS feed Easy Print E-Mail this Message

Related News
TSMC, Samsung Take Different Approaches For 7nm
TSMC, Mentor Graphics To Enable Design and Verification Tools for New InFO Technology Variants
TSMC To Build New Fab for 3nm
ARM Physical IP for TSMC 7nm Process Technology Now Available
TSMC And IBM Detail Their 7nm Progress At 2016 IEDM
TSMC To Relabel Manufacturing Process As 12nm
TSMC, GlobalFoundries/Samsung To Present Their 7nm Platforms At IEDM
TSMC Sees Strong Quarter On Smartphone Chip Demand
TSMC To Use Different Processes And 3D Packages Across Future Design Platforms
TSMC 7nm Volume Production To Start In 1Q18
TSMC Foundry Market Share Drops in 2016
Samsung, TSMC And Intel Set To Expand Their Chip Production Capacities In 2H

Most Popular News
 
Home | News | All News | Reviews | Articles | Guides | Download | Expert Area | Forum | Site Info
Site best viewed at 1024x768+ - CDRINFO.COM 1998-2017 - All rights reserved -
Privacy policy - Contact Us .