Saturday, December 20, 2014
Search
  
Submit your own News for
inclusion in our Site.
Click here...
Breaking News
T-Mobile to Pay $90 Million To Settle Case With FCC
New Trojan Targetted Banks Wordlwide
FBI Confirms North Korea Was Behind Sony Hack
Apple Responds To BBC's Allegations Over Working Conditions In Chinese Factory
BlackBerry Returns To Cash Flow
Comparison: Quantum Dot Vs. OLED Displays
Toshiba and SK Hynix Reach Settlement in Lawsuit Ahead Of CES
Google Concerned About MPAA's Actions To Revive SOPA
Active Discussions
Digital Audio Extraction and Plextools
Will there be any trade in scheme for the coming PSP Go?
Hello, Glad to be Aboard!!!
Best optical drive for ripping CD's? My LG 4163B is mediocre.
Hi All!
cdrw trouble
CDR for car Sat Nav
DVD/DL for Optiarc 7191S at 8X
 Home > News > General Computing > GLOBALF...
Last 7 Days News : SU MO TU WE TH FR SA All News

Friday, June 11, 2010
GLOBALFOUNDRIES Releases Silicon-Validated Library for Pattern-Based SoC DFM Verification at 28nm and Below


GLOBALFOUNDRIES today announced the availability of a new silicon-validated solution to help the company' s customers accelerate time-to-volume for complex SoC designs at 28nm and beyond.

Called DRC+, the technique goes beyond standard Design Rule Checking (DRC) and uses two-dimensional shape-based pattern-matching to enable a 100-fold speed improvement in identifying complex manufacturing issues without sacrificing accuracy.

"As the industry continues to adopt more advanced process technology, it becomes increasingly critical for foundries to provide customers with the tools to ensure first-silicon success," said Mojy Chian, senior vice president of design enablement at GLOBALFOUNDRIES. "Standard DRC is challenged to capture design issues that could impact the manufacturability of an integrated circuit. With DRC+, we are improving upon the traditional approach and giving customers increased visibility into potential manufacturability issues, earlier in the design flow."

Until now, a designer has only had two primary options for identifying DFM issues during the SoC design cycle: run accurate but computationally intensive simulations based on numerical algorithms, or rely on metrology measurements directly from the fab. Attempts have been made to improve upon standard DRC with additional rules, but these approaches have had mixed success. For example, some have proposed the use of restrictive design rules that only allow highly regular structures for layout, avoiding problematic two-dimensional geometries altogether. The potential drawback is that designers cannot effectively optimize their circuits to meet application requirements with overly constrained design rules.

DRC+ takes a different approach. Instead of restricting the flexibility of designers, the technique augments standard DRC by applying rapid two-dimensional shape-based pattern matching to identify problematic configurations that could be difficult to manufacture. The tool then returns specific feedback to designers on how to resolve these issues.

In tests run at GLOBALFOUNDRIES, DRC+ identified known problem patterns at speeds comparable to traditional DRC verification engines-leading to a 100-fold improvement in the speed of hotspot detection, without sacrificing accuracy.

DRC+ augments and completes the overall DFM solution provided by GLOBALFOUNDRIES, together with rule-based DFM verification and model-based litho/etch and CMP simulators, which can identify new yield-detracting patterns, as process conditions and design styles change over time, during technology development. As the process matures, DRC+ pattern-matching-based verification at the full-chip level can then be used to achieve increasing performance improvements, at the highest level of accuracy. By improving verification speed, DRC+ can have a direct impact on the ability to rapidly ramp a product to volume and accelerate time-to-market.

The DRC+ verification flow has been successfully used on several 32nm production IC designs and libraries of yield-detractors patterns for 28nm technology nodes are currently available from GLOBALFOUNDRIES for foundry customers.

Representatives from GLOBALFOUNDRIES, Cadence, and Mentor will be on hand at the upcoming Design Automation Conference (DAC) to provide further details on the DRC+ technique.


Previous
Next
Kinect for Xbox 360 is Official Name of Microsoft's Controller-Free Game Device        All News        Motorola and Research In Motion Announce Settlement and License Agreement
IBM, ARM, Samsung, GLOBALFOUNDRIES and Synopsys Announce Delivery of New Chip Platform     General Computing News      Oerlikon Systems Wins Significant Order from World?s Largest Semiconductor Foundry

Get RSS feed Easy Print E-Mail this Message

Related News
Globalfoundries Invests In MRAM Maker Everspin
Glonbalfoundries Buy IBM's Micorelectronics Business
IBM Talks With Globalfoundries Stall Over Price: report
IBM May Sell Chip-Making Unit to Globalfoundries: report
GLOBALFOUNDRIES Introduces 55nm Automotive-Specific Semiconductor Manufacturing Platform
Toshiba Joins GLOBALSOLUTIONS Ecosystem
Samsung Works With GLOBALFOUNDRIES On 14 nm FinFET Offering
Globalfoundries To Buy IBM chip-making Business: report
AMD Amends Wafer Supply Agreement With GLOBALFOUNDRIES
Toshiba And GLOBALFOUNDRIES To Work Together On FFSA Manufacturing
Cadence and GLOBALFOUNDRIES Announce First Test Chip Featuring ARM Cortex-A12 Processor in 28nm-SLP Process
GLOBALFOUNDRIES Demonstrates Model for Next-Generation Chip Packaging Technologies

Most Popular News
 
Home | News | All News | Reviews | Articles | Guides | Download | Expert Area | Forum | Site Info
Site best viewed at 1024x768+ - CDRINFO.COM 1998-2014 - All rights reserved -
Privacy policy - Contact Us .