Tuesday, February 28, 2017
Search
  
Submit your own News for
inclusion in our Site.
Click here...
Breaking News
MWC 2017: Porsche Design Reveals 2-in-1 with Windows 10
GDC 17: Google Announces New Games For Daydream
Oppo Brings 5X Optical Zoom To Dual-camera Smartphones
Kingston Ships 2TB USB Flash Drive
One-Blue Lowers Blu-ray Licensing Fees
Twitch to Sell Video Games on Streaming Site
Personal Computing Devices Outlook Remains Mildly Negative, Detachable Tablets And Convertible Notebooks See Growth
Gionee Launch New Selfie-focused A1 And A1 Plus Smartphones
Active Discussions
Which of these DVD media are the best, most durable?
How to back up a PS2 DL game
Copy a protected DVD?
roxio issues with xp pro
Help make DVDInfoPro better with dvdinfomantis!!!
menu making
Optiarc AD-7260S review
cdrw trouble
 Home > News > General Computing > GLOBALF...
Last 7 Days News : SU MO TU WE TH FR SA All News

Friday, June 11, 2010
GLOBALFOUNDRIES Releases Silicon-Validated Library for Pattern-Based SoC DFM Verification at 28nm and Below


GLOBALFOUNDRIES today announced the availability of a new silicon-validated solution to help the company' s customers accelerate time-to-volume for complex SoC designs at 28nm and beyond.

Called DRC+, the technique goes beyond standard Design Rule Checking (DRC) and uses two-dimensional shape-based pattern-matching to enable a 100-fold speed improvement in identifying complex manufacturing issues without sacrificing accuracy.

"As the industry continues to adopt more advanced process technology, it becomes increasingly critical for foundries to provide customers with the tools to ensure first-silicon success," said Mojy Chian, senior vice president of design enablement at GLOBALFOUNDRIES. "Standard DRC is challenged to capture design issues that could impact the manufacturability of an integrated circuit. With DRC+, we are improving upon the traditional approach and giving customers increased visibility into potential manufacturability issues, earlier in the design flow."

Until now, a designer has only had two primary options for identifying DFM issues during the SoC design cycle: run accurate but computationally intensive simulations based on numerical algorithms, or rely on metrology measurements directly from the fab. Attempts have been made to improve upon standard DRC with additional rules, but these approaches have had mixed success. For example, some have proposed the use of restrictive design rules that only allow highly regular structures for layout, avoiding problematic two-dimensional geometries altogether. The potential drawback is that designers cannot effectively optimize their circuits to meet application requirements with overly constrained design rules.

DRC+ takes a different approach. Instead of restricting the flexibility of designers, the technique augments standard DRC by applying rapid two-dimensional shape-based pattern matching to identify problematic configurations that could be difficult to manufacture. The tool then returns specific feedback to designers on how to resolve these issues.

In tests run at GLOBALFOUNDRIES, DRC+ identified known problem patterns at speeds comparable to traditional DRC verification engines-leading to a 100-fold improvement in the speed of hotspot detection, without sacrificing accuracy.

DRC+ augments and completes the overall DFM solution provided by GLOBALFOUNDRIES, together with rule-based DFM verification and model-based litho/etch and CMP simulators, which can identify new yield-detracting patterns, as process conditions and design styles change over time, during technology development. As the process matures, DRC+ pattern-matching-based verification at the full-chip level can then be used to achieve increasing performance improvements, at the highest level of accuracy. By improving verification speed, DRC+ can have a direct impact on the ability to rapidly ramp a product to volume and accelerate time-to-market.

The DRC+ verification flow has been successfully used on several 32nm production IC designs and libraries of yield-detractors patterns for 28nm technology nodes are currently available from GLOBALFOUNDRIES for foundry customers.

Representatives from GLOBALFOUNDRIES, Cadence, and Mentor will be on hand at the upcoming Design Automation Conference (DAC) to provide further details on the DRC+ technique.


Previous
Next
Kinect for Xbox 360 is Official Name of Microsoft's Controller-Free Game Device        All News        Motorola and Research In Motion Announce Settlement and License Agreement
IBM, ARM, Samsung, GLOBALFOUNDRIES and Synopsys Announce Delivery of New Chip Platform     General Computing News      Oerlikon Systems Wins Significant Order from World?s Largest Semiconductor Foundry

Get RSS feed Easy Print E-Mail this Message

Related News
GLOBALFOUNDRIES Invests For Capacity Growth In The US, Germany, China and Singapore
KAIST Sues Samsung, Qualcomm And Globalfoundries Over FinFET Patent Infringement
TSMC, GlobalFoundries/Samsung To Present Their 7nm Platforms At IEDM
GLOBALFOUNDRIES Debuts 7nm FinFET Technology, Embedded MRAM
FD-SOI Could Emerge As A Cheaper Alternative To FinFET Processes
GLOBALFOUNDRIES Extends FDX Roadmap with 12nm FD-SOI Technology
AMD Enters New Wafer Supply Agreement With GLOBALFOUNDRIES
GLOBALFOUNDRIES Releases 130nm SiGe RF Technology For Wireless Network Communications
SUNY Poly and GLOBALFOUNDRIES Announce $500M Research ProgramTo Accelerate Chip Technology
GLOBALFOUNDRIES Launches High-Performance ASIC Offering on 14nm FinFET Process
GlobalFoundries And AMD Achieve 14nm FinFET Technology Success
Globalfoundries Said To Move To 10nm Development On Its Own

Most Popular News
 
Home | News | All News | Reviews | Articles | Guides | Download | Expert Area | Forum | Site Info
Site best viewed at 1024x768+ - CDRINFO.COM 1998-2017 - All rights reserved -
Privacy policy - Contact Us .