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Friday, June 11, 2010
Samsung Qualifies 32nm Low Power High-K Metal Gate Logic Process


Samsung's foundry business, Samsung Foundry, has qualified 32nm low-power (LP) process with high-k metal gate (HKMG) technology.

The company said that the process has successfully completed reliability testing at Samsung Foundry's 300-millimeter logic fabrication line, the S Line, in Giheung, Korea and, is now ready for production of customer designs. Samsung Foundry is poised to begin volume manufacturing of chips designed to meet the media intensive, energy-efficient requirements of next-generation mobile consumer electronics.

Samsung Foundry, together with the IBM Joint Development Alliance (JDA), has tuned its 32nm LP HKMG gate-first process node to deliver a cutting-edge process platform with double the logic density of 45nm processes through minimized restrictive design rules.

"This result is another significant milestone in our strategy to provide leadership foundry process technology fully integrated with state-of-the-art design solutions for low power system-on-chip (SoC) design," said Stephen Woo, executive vice president and general manager, System LSI Division, Samsung Electronics. "Collaborating with several key partners, we have been able to take HKMG from development to implementation in a production environment. Our customers can now seamlessly integrate their design innovations with the most advanced 32nm LP HKMG process technology, design tools, IP and manufacturing to accelerate time to market for their leading edge mobile silicon solutions."

"Congratulations to Samsung on being the first foundry to demonstrate SoCs using high-k/metal gate technology. This important milestone represents the culmination of collaboration by the IBM technology development alliance to deliver the competitive, low power' gate first' high-k technology - ideal for the emerging next-generation mobile applications," said Gary Patton, vice president for IBM's Semiconductor Research and Development Center.

As part of the qualification process, Samsung Foundry designed and manufactured a 32nm LP SoC that shows 30 percent dynamic power reduction and 55 percent leakage power reduction when compared to the SoC design implemented at 45nm LP at the same frequency. Samsung Foundry was able to reach these significant power reduction numbers due to its gate-first HKMG implementation.

In developing the 32nm LP process, Samsung Foundry worked in close engineering partnership with its ecosystem partners. The partner IP successfully integrated and silicon proven in this SoC includes ARM 1176 core, ARM physical IP comprising of standard cells, memory compilers and I/Os and Synopsys' USB 2.0 OTG.

Samsung Foundry worked with EDA partners including Synopsys, Cadence Design Systems and Mentor to incorporate advances into the design flow for 32nm LP such as:

- Advanced low power techniques including power gating, multi-threshold voltages, multi-channel lengths and adaptive body biasing techniques were used to reduce leakage power
- Statistical Static Timing Analysis (SSTA) was used to effectively address variation and reduce timing margins
- Various cell and chip level DFM techniques were used to improve manufacturability

Samsung Foundry's 32nm LP HKMG process technology has been developed to offer its customers shrinkable design rules and a smooth migration path to 28nm LP.


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