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Wednesday, May 27, 2009
Rambus Unveils New Innovations for Next Generation DDR4 Memory

Rambus today unveiled a set of innovations that can advance computing main memory beyond current DDR3 data rate limits to 3200Mbps.

The company hopes that the industry will adopt its new technologies as part of the pending DDR4 DRAM standard.

The new techniques are definitely promising but it is not clear whether they will be widely used in the standards for the next generation of DRAM memory. Rambus has been in ligitations with the largest DRAM makers in the last 10 years and is also not part of the JEDEC group, which defines the DRAM standards.

"Product advancements in multi-core computing, virtualization and chip integration put ever-increasing demands on the memory sub-system, a key performance limiter in today?s performance computing systems," said Craig Hampel, Rambus Fellow. "This collection of breakthrough innovations from Rambus allows for memory systems that are better suited for the bandwidth and workloads of these throughput-oriented multi-core processors, increasing the design and solution space for future main memory to enable a new generation of computing platforms."

The Rambus key innovations to advance the main memory roadmap include:

- FlexPhase Technology - introduced in the XDR memory architecture, can enable higher data rates compared to direct strobing technology used in DDR3;

- Near Ground Signaling - supports high performance at greatly reduced IO power, allowing operation at 0.5V while still maintaining robust signal integrity;

- FlexClocking Architecture - introduced in Rambus? Mobile Memory Initiative, reduces clocking power by eliminating the need for a DLL or PLL on the DRAM;

- Module Threading - increases memory efficiency and reduces DRAM core power, and when combined with Near Ground Signaling and FlexClocking technology, can cut total memory system power by over 40%;

- Dynamic Point-to-Point (DPP) - provides a path for capacity upgrades without compromising performance through robust point-to-point signaling.

Details of these techniques and how they reduce limitations found in current memory solutions have been captured in a whitepaper, "Challenges and Solutions for Future Main Memory" that is available for download at

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