Saturday, August 23, 2014
Search
  
Submit your own News for
inclusion in our Site.
Click here...
Breaking News
German Regulator Will Pursue Complaint Against Publishers
IBM Tries To Strengthen Its Presence In China With Local Vendor Deal
Demand For iPhone 6 Screens Add Perssure To Supply Chain
Intel Highlights Its Wireless Computing Plans
Ouya Parners With Xiaomi On Games
Sony Offers New Smart Tennis Sensor
Microsoft to Announce Windows 9 on September Event: report
Acer Unveils New Chromebox CXI and Chromebook 11
Active Discussions
help questions structure DVDR
Made video, won't play back easily
Questions durability monitor LCD
Questions fungus CD/DVD Media, Some expert engineer in optical media can help me?
CD, DVD and Blu-ray burning for Android in development
IBM supercharges Power servers with graphics chips
Werner Vogels: four cloud computing trends for 2014
Video editing software.
 Home > News > PC Parts > NEC, To...
Last 7 Days News : SU MO TU WE TH FR SA All News

Thursday, December 18, 2008
NEC, Toshiba Develop Cost-effective 32nm CMOS Platform Technology


Toshiba has developed a cost-effective 32nm CMOS platform technology that offers higher density and improved performance while halving the cost per function from 45nm technology.

The platform was achieved by application of advanced single exposure lithography and gate-first metal gate/high-K process technology. This technology enables a 0.124μm2 SRAM cell and a gate density of 3,650 gate/mm2. This SRAM cell is the smallest yet achieved in the 32nm generation. The platform technology is based on a 32nm process technology developed jointly with NEC Electronics.

Advanced semiconductor process migration faces challenges to achieve both cost competitiveness and enhanced performance for stricter design rules. This requires technological optimization in lithography and patterning integration, materials, and device design.

Realizing the strict design rule in the 32nm generation was originally seen as requiring dual exposure technology in the lithography process, which would result in higher process costs due to increased process steps, and in degraded manufacturing yields owing to increased process dusts. Toshiba realized an architecture based on single exposure lithography by applying ArF immersion lithography with a NA 1.3 and over, and by optimizing the lithography illumination conditions.

The development work also demonstrated that application of a metal gate/high-K not only boosts transistor performance but also reduces threshold voltage mismatch, which affects stable operation of SRAM and logic circuits. In addition, a bent-shaped type cell was selected for layout optimization, which also contributed to reduce threshold voltage mismatch.

By adopting this approach, Toshiba realized a 32nm CMOS platform design that reduces cost per function by 50% from 45nm technology, an achievement that would have been impossible with conventional poly/SiON and double patterning.

Toshiba said that it would further enhance development of the new platform.

The achievement was introduced today at the International Electron Devices meeting (IEDM) in San Francisco, CA.

New Platform Technology for 40nm CMOS Process

At the same event, Toshiba announced a 40nm CMOS platform technology based on 45nm process technology co-developed with NEC Electronics. The new platform fabricates SOC for power-critical mobile applications that consume less than half the power of 65nm generation LSI. The company also announced that it expects to deploy the technology on samples in the fourth quarter of FY2008, and in mass production in the second quarter, FY2009.

Advanced mobile application requires reduced chip size and lower power consumption. Process migration is a solution to meet the demand, however, shorter channel length tends to cause current leakage. Both reduction of power consumption and chip size shrinkage require controlling channel impurity concentration and fining layout.

Toshiba has established and applied new platform technology for a new activation sequence using flash lamp anneal, optimizing impurities in the ion implantation process, and applying Hafnium incorporated insulators and DFM (design for manufacturing) technologies. Doubling the flash lamp anneal process boosted both the PMOS and NMOS performance. Doping germanium with nitrogen in the ion implantation process minimized concentration in the channel area, which contributes to higher transistor performance. Hafnium incorporated insulators improve drive current by increasing threshold voltage without excess concentration of channel impurities. Application of DFM technologies enabled aggressively scaled layout with lower lithographic defects.


Previous
Next
AOL Launches New Version of Web Mail        All News        Philips Reaches Consensus with Ritek and CMC
Sony Pre-loading Music and Movies On Microvault Flash Drives     PC Parts News      Toshiba Launches 512GB Solid State Drive and Next-Generation SSD family using 43nm MLC NAND

Get RSS feed Easy Print E-Mail this Message

Related News
Toshiba Responds To Samsung, Introduces 3-Bit SSD
Toshiba's New Wearable Wristband Fitness Tracker Runs Two Weeks without Recharging
Toshiba Launches 8 Megapixel CMOS Image Sensor for Smartphones
Toshiba Launches 5TB Surveillance HDD
Toshiba to Release Wearable Biological Sensor
Samsung, Intel, Dell, Boradcom Team Up On Standards For Internet of Things
Toshiba Introduces Storage Place Solution
Toshiba Brings Suit Against Powerchip for NAND Flash Memory Patent Infringement
Toshiba Debuts the Satellite Radius Multimode Laptop, New Detachable Notebooks And Windows 8.1 Tablets
Toshiba Announces 5TB, 7,200 RPM Enterprise HDD
SanDisk and Toshiba License Memory Technology IP
Toshiba to Start Vegetable (!) Production at New Factory

Most Popular News
 
Home | News | All News | Reviews | Articles | Guides | Download | Expert Area | Forum | Site Info
Site best viewed at 1024x768+ - CDRINFO.COM 1998-2014 - All rights reserved -
Privacy policy - Contact Us .