Spansion today unveiled plans for its upcoming MirrorBit ORNAND2 product family, designed to support 25 percent faster write performance and up to twice the read performance at a significantly smaller die size than today's floating-gate NAND.
With the MirrorBit ORNAND2 family, Spansion plans to further diversify its product portfolio to address a broader portion of the high-value wireless and embedded markets, with initial single chip densities ranging from 1 Gigabit (Gb) to 4 Gigabits (Gb) at both 1.8 and 3.0 volts using a Single Level Cell (SLC) architecture.
The MirrorBit ORNAND2 product family leverages the company's proprietary MirrorBit charge-trapping technology and features a SONOS-like cell connected in a true NAND array. The technology features 25 percent fewer process steps than the first generation MirrorBit ORNAND and MirrorBit NOR solutions, enabling significantly lower cost.
Spansion's MirrorBit ORNAND2 products based on an SLC architecture, 3.0V operating voltage, and an industrial temperature range, are suited for embedded applications such as plug-in the wall, car multimedia, networking infrastructure, and industrial control systems. Spansion expects to integrate "managed NAND" controller and interface functionalities with MirrorBit ORNAND2 memory on a single chip, for the creation of a full product family of differentiated solutions. The integration of a "managed NAND" interface will help simplify system level design to complement industry-standard chipsets and microcontrollers.
In the handset segment, Spansion plans to expand its product portfolio with the addition of MirrorBit ORNAND2 solutions.