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Tuesday, December 18, 2007
Toshiba's Next-generation HDTVs to Use XDR DRAM


Rambus has announced that Toshiba has licensed its XDR memory controller interface cell (XIO) and XDR memory controller (XMC) for next-generation high-definition television (HDTV) chipsets.

The XIO and XMC will be implemented in Toshiba?s 65nm process. Operating at 4.8Gbps, the XDR memory architecture will allow Toshiba?s HDTV chipset to deliver higher image processing performance in its customers? HDTVs.

"HDTVs now require as much memory bandwidth as many PCs in order to deliver the advanced features consumers demand," said Hideki Moriyama, Deputy General Manager of the System LSI Division at Toshiba's Semiconductor Company. "With the XDR memory architecture, we are able to achieve both superior performance and a reduced bill of materials for our customers? HDTV applications."

The XDR memory architecture uses patented Rambus innovations such as Octal Data Rate (ODR) technology, Differential Rambus Signaling Level (DRSL), and FlexPhase circuits to deliver high bandwidth while using fewer DRAM devices than industry-standard memory solutions. Higher memory performance as delivered by the XDR architecture enables the advanced features of next-generation HDTVs such as 1080p+ resolution, 120Hz refresh rates, 12-bit color, multiple full HD Picture-in-Picture (PiP) data streams, and advanced image enhancement algorithms.


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