Tuesday, January 16, 2018
Search
  
Submit your own News for
inclusion in our Site.
Click here...
Breaking News
BlackBerry Jarvis Will Protect Your Connected Car
iPhone Assembler Hon Hai to Get OLEDs from Sharp
Google's Map to Return to China: report
Fake Spectre and Meltdown Patch Pushes Malware
HTC U11 Eyes Comes With Dual front Cameras and Large Battery
IBM Researchers Bring Memory Disaggregation to Data Centers
Fujitsu and The Shinano Mainichi Shimbun Create AI-Based System to Automate Article Summaries
UMC Countersuits Micron
Active Discussions
Which of these DVD media are the best, most durable?
How to back up a PS2 DL game
Copy a protected DVD?
roxio issues with xp pro
Help make DVDInfoPro better with dvdinfomantis!!!
menu making
Optiarc AD-7260S review
cdrw trouble
 Home > News > PC Parts > Rambus ...
Last 7 Days News : SU MO TU WE TH FR SA All News

Wednesday, November 28, 2007
Rambus Paves the Way For Terabyte Bandwidth Memories


Rambus today unveiled technologies that could enable the development of new memory that will facilitate data rates of a terabyte per second.

Today's multi-core processor-based systems require greatly increased memory performance over systems built around single-core processors. Delays between microprocessors and external DRAMs have long been a bottleneck in system performance. As an example, graphics processors currently require as much as 128GBytes/s of memory bandwidth and are targeting 500 GBytes/s in the near future. The current generation of gaming systems uses 25-50 GBytes/s of memory bandwidth. Over the next 4-5 years, graphics and game consoles will push memory bandwidth needs towards 1 TByte/s. With the technology developed through the "Terabyte Bandwidth Initiative," Rambus said that it would dramatically increase the data rate of memory.

"Continuing the Rambus tradition of innovation, our engineers and scientists have pioneered new technologies that will enable terabyte per second memory architectures for gaming, computing and consumer electronic systems of the next decade," said Kevin Donnelly, senior vice president of engineering at Rambus Inc.

Rambus? Terabyte Bandwidth Initiative includes new innovations for a new generation of memory systems, such as:

- 32X data rate ? 32 data bits per input clock cycle;
- Fully Differential Memory Architecture (FDMA) ? The industry?s first differential signaling for both data and command/address (C/A);
- FlexLink C/A ? The industry?s first full-speed, point-to-point C/A link.

Rambus' 32X Data Rate technology transmits 32 bits of data per clock cycle on each I/O. Conventional double data rate memory systems transfer two bits of data, per I/O, every clock cycle. While double data rate memory architectures can achieve an one gigabit per second transfer rate with a 500 MHz clock, 32X Data Rate enables a 16Gbps signaling rate using the same 500 MHz clock.

In fully differential memory architecture (FDMA), both the data path and command/address channel employ differential signaling for robust communications between the memory controller and the DRAM. Rambus pioneered high speed differential memory signaling by transitioning the data signals from a single ended architecture to a differential scheme and used the signalling technique in its XDR DRAM design. Differential signaling inherently reduces interference noise, such as simultaneous switching output (SSO), crosstalk, and electromagnetic interference (EMI). Rambus has expanded the use of differential signaling in the Terabyte Bandwidth Initiative to include not only the data signals, but also the command/address signals.

The third featured innovation of the Terabyte Bandwidth Initiative is FlexLink C/A. FlexLink C/A implements the industry's first full-speed, scalable, point-to-point command/address link. Operating at 16Gbps, FlexLink C/A reduces the required number of signal pins on both the DRAM and the memory controller. In contrast with a 1Gbit DDR2 device which requires 28 wires to connect the command/address link between the memory controller and the DRAM, FlexLink C/A implements a full 16Gbps command/address link with only two connections. This serial link also provides fine access and scalable capacity through a single command/address link per DRAM. FlexLink C/A's serial connectivity also delivers reduced area, power and pin count and lowers overall system costs.

At the Tokyo demonstration held today, Rambus showcased a 65nm controller linked to two 65nm RAM devices with aggregate throughput of up to 32 Gbytes/s to each memory chip.


Previous
Next
Facelift for Lite-On EZ-DUB        All News        DaTARIUS Opens First European HD DVD Class-A Verification Laboratory
Asus Optimistic About Eee PC Sales     PC Parts News      Fujitsu to Release 2.5" HDD with 320 GB Capacity

Get RSS feed Easy Print E-Mail this Message

Related News
CES 2018: HyperX Unveils Infrared Synchronized DDR4 RGB Memory, Wireless Headset and RGB Gaming Gear
China Accelerates Domestic Memory Chips Fabrication
Corsair Launches 4GHz DDR4 SODIMM 32GB Memory Kit
Crucial Releases 128GB DDR4 LRDIMM Server Memory
G.Skill Unveils Trident Z DDR4-4400 32GB CL19 Kit
Samsung's 16Gb GDDR6 Memory and New Exynos 9 Series 9810 Mobile Processor Win CES 2018 Innovation Awards
G.SKILL Releases Fastest 32GB Trident Z RGB Memory Kit at DDR4-4266MHz
G.SKILL Releases New DDR4 for Intel Coffee Lake Platform
Micron to Bring GDDR6N Memory to Networking Devices
Rambus Runs First DDR5 Silicon in its Labs
Micron Brings LPDDR4 and GDDR6 Memory to Autonomous Vehicles
G.Skill Releases 16 GB DDR4-4600 1.5v Kit for the Kaby Lake-X Platform

Most Popular News
 
Home | News | All News | Reviews | Articles | Guides | Download | Expert Area | Forum | Site Info
Site best viewed at 1024x768+ - CDRINFO.COM 1998-2018 - All rights reserved -
Privacy policy - Contact Us .