The JEDEC Solid State Technology Association announced today that it has completed development and publication of the DDR3 (Double Data Rate 3) memory device standard.

The new DDR3 Synchronous DRAM (Dynamic Random Access Memory) standard is expected to be broadly adopted in the industry, providing significant improvements in performance at reduced power ? as compared to prior generation technologies (SDR, DDR1, DDR2). Key technology and functional improvements include a 1.5V power supply, increased operating temperature range, memory device reset, burst chop, dynamic on-die termination, output driver calibration, write leveling and other features to enable high speed operation and broad applicability in loose device and module applications.

Intel Director of Platform Memory Operations and JEDEC Board member Paul Fahey stated that "the DDR3 standard will serve as the lynchpin for developing a new generation of memory solutions that address demands for both lower power and high performance. DDR3 will be an essential ingredient in future mobility platforms and those applications requiring the highest performance, such as video-on-demand, encoding and decoding, gaming and 3D visualization."

In addition to the introduction of the DDR3 Device Specification, JEDEC completed publication and release of a wide range of DDR3-based memory modules, including Registered DIMMs, Unbuffered DIMMs, SO (Small Outline) DIMMs and other module types and configurations intended for use in desktop, mobile and server computer systems, telecommunications, point of sale and a wide range of other electronic products. Support devices have also been developed and include registers, PLL?s (phase locked loops) and other interface devices optimized for use with the new technology.

The DDR3 standard is intended to operate over a performance range from 800 to 1600 MT/s (million transfers per second) and device densities from 512 Mb to 8 Gb in monolithic and stacked packages.

JEDEC also announced a DDR3 Technical Workshop, to be held in San Jose California on October 3-4, 2007. This workshop will include technical presentations by major DRAM and chipset producers, and is intended to provide adopters with a detailed understanding of the DDR3 specification, operational characteristics, changes from prior generation devices, application guidelines, an overview of JEDEC memory modules and other critical information related to this memory technology.