Saturday, January 24, 2015
Search
  
Submit your own News for
inclusion in our Site.
Click here...
Breaking News
Sony Postpones Earnings Announcement
January Windows 10 Build Released Through The Windows Insider Program
Flexible Computers Are Stil Away From Reality
China Denies Microsoft Outlook Hacking Allegations
A Look at Microsoft's New Spartan Browser
JOLED Joint Venture Company Established
Samsung Engineers Develop Wearable Sensor for Stroke Detection
Skype To Be Part Of Windows 10
Active Discussions
HELP!!!
full screen wide screen
UDF errors
Hi
The Simplest Way to Download KODAK HERO 7.1 Driver
About the restriction problem of chapter quantity in DVD
Booktype utilities for LiteON and OEM DVD Recorders
downgrade a nero vision 5 project to nero vision 2
 Home > News > PC Parts > Fujitsu...
Last 7 Days News : SU MO TU WE TH FR SA All News

Monday, June 18, 2007
Fujitsu Details Advanced 45nm Technology for Logic Chips


Fujitsu today announced their development of a platform technology for 45 nanometer (45nm) generation LSI logic chips, which combines technologies for low power consumption and high-performance interconnect.

Fujitsu said that compared to previous 45nm technologies on record, the new platform reduces the leakage current that occurs when current is wasted in wait states to one-fifth that of previous levels and reduces interconnect-induced lag times by approximately 14%. The new technology will enable Fujitsu to offer LSI logic chips that feature even higher speeds, smaller size and lower power consumption than currently available.

Details of the new technology were presented at the 2007 Symposium on VLSI Technology.

In order to heighten integration levels of LSIs, with each new generation of devices, there is a need to shorten the gate length of each transistor and make the spaces between interconnects narrower. In addition, to achieve high speeds there is a need to minimize the time lag from interconnects between the hundreds of millions of individual transistors within the LSI chip.



When a the gate length of a transistor is shortened, a problem that exists is increased power consumption attributable to increased leakage current between the transistor's source and drain when no signal voltage is applied at the gate - for example, when a mobile phone is on standby mode awaiting calls and no operation processing is underway.

For the 45nm generation, both the width of interconnects and the spaces between interconnects, are at the smallest 65nm. In addition to an increase of interconnect resistance due to miniaturization, if the insulating layer's dielectric constant stays the same as the previous generation, interconnect capacitance will increase, thereby resulting in increased interconnect lag and thus necessitating a material with lower dielectric constant.

Fujitsu researchers found that forming shallower source and drain regions is an effective way to reduce leakage current.



However, simply making them shallower also increases resistance at the source and drain regions, thereby degrading transistor performance. To counteract this, Fujitsu researchers developed a new annealing technology called millisecond annealing (MSA). Compared to previous annealing, Fujitsu's millisecond annealing technology uses higher temperatures thus enabling reduction of resistance, and because the annealing time is brief it possible to form shallow sources and drain regions and thereby reduce leakage current.

Fujitsu researchers also used nano-clustering silica (NCS), which has a dielectric constant (k) of 2.25 - the lowest of any insulating film reported to date - in a lower interconnect region suitable for the smallest interconnect spaces.

NCS is an insulating material pocked with miniscule holes, enabling both a low dielectric value and high mechanical strength simultaneously. Fujitsu introduced NCS on a partial basis beginning with the 65nm generation. However, for the 45nm generation, the company is using NCS not just within a given interconnect layer but also between different layers to further reduce interconnect capacitance.

"The new technique is highly effective in limiting transistor resistance, reducing leakage current to one-fifth that of previous levels, thereby enabling advantages such as extending mobile phone maximum standby (wait) time up to five-fold," said Fujitsu in a statement.

In addition, by utilizing high-performance interconnect technology Fujitsu was able to achieve a 14% reduction in interconnect lag time in comparison to standard 45nm generation interconnect technologies in the International Technology Roadmap for Semiconductors.

Fujitsu is targeting 2008 to incorporate these technologies into LSIs that are suited for mobile devices.


Previous
Next
Blockbuster to Focus on Blu-Ray        All News        EC Cancels Anti-dumping Tariffs On Taiwanese Optical Discs
G.Skill Begins Sales of DDR3-1333 CL8 and CL9 Memory kits     PC Parts News      Google, Intel Launch Energy Efficiency Program

Get RSS feed Easy Print E-Mail this Message

Related News
Fujitsu Extends Its LIFEBOOK Line-up
Fujitsu Develops Wearable For Safer Driving, Technology That Identifies PC User Behaviors Vulnerable To Cyber Attacks
Fujitsu Develops Ring-Type Wearable Device That Lets You Write In The Air
Fujitsu Signs Collaborative Research Agreements with Medical Research Institutions
Fujitsu Introduces Two Tablets for Businesses
Fujitsu Develops Sensing Middleware to Simplify Development of Sensing Applications
Fujitsu Develops LED Lighting Technology that "Shines" Data on Objects
Fujitsu Develops Design Technology for Allocating LTE-Advanced Base Stations
Fujitsu Launches Petabyte-scale New Hyper-scale Storage ETERNUS CD10000
Fujitsu Boosts Lineup of Smartphones and Tablets for the Enterprise
Fujitsu Develops Fast Recovery Process for Multiple Disk Failures
Fujitsu Relases New Extreme Series SSDs

Most Popular News
 
Home | News | All News | Reviews | Articles | Guides | Download | Expert Area | Forum | Site Info
Site best viewed at 1024x768+ - CDRINFO.COM 1998-2015 - All rights reserved -
Privacy policy - Contact Us .