Taiwan Semiconductor Manufacturing Company has announced that it would complete 45nm technology qualification and enter production as early as September 2007.
The new 45nm process combines advanced 193nm immersion photolithography, competitive performance-enhancing silicon strains, and extreme low-k (ELK) inter-metal dielectric material.
TSMC?s 45nm low power process (LP) provides twice the density of 65nm with significantly lower power and manufacturing cost per die. With a high gate density and high-density 6T SRAM cell, more than 500 million transistors will easily fit into a 70mm2 die area. End products are expected to achieve 40 percent greater functionality or 40 percent smaller die size, with reduced power consumption. These factors are particularly crucial for system on chip (SoC) designs with an ever-smaller footprint for cell phones, portable media players, PDAs and other handheld devices.
TSMC?s 45nm general purpose and high performance process (GS) provides more than double the density and a greater than 30 percent speed enhancement over the previous generation at similar leakage power, which is especially critical to support applications in PC, networking, and wired communication.
Nvidia is likely to be the first customer of TSMC to introduce production on this half node geometry. The company has been cooperating with TSMC for a long time and it has reportedly started pilot runs on 55nm in early 2007. The graphics chip maker should introduce 55nm in volume production in the first quarter of 2008.
According to reports, AMD has also started pilot runs on 55nm.
Currently, the most advanced process used for production is the 65nm process. Intel is expected to begin producing chips at 45nm later this year.