Taiwan Semiconductor Manufacturing Co. (TSMC), the world's largest contract chip maker, is offering companies a way to make chips that are faster, consume less power and cost less than is possible with 65-nanometer process technology.

TSMC today unveiled its 55nm process technology, a 90% linear-shrink process from 65nm including I/O and analog circuits.

The process delivers significant die cost savings from 65nm, while offering the same speed and 10 to 20% lower power consumption, according to TSMC.

"Because the 55nm process is a direct shrink, IP providers can leverage existing libraries and port their 65nm designs with minimal risk and effort," the company said in a statement. The 55nm logic family includes general purpose (GP) and consumer (GC) platforms. Initial production of the 55GP begins this quarter, followed later in the year by 55GC.

Nvidia is likely to be the first customer to introduce production on this half node geometry. The company has been cooperating with TSMC for a long time and it has reportedly started pilot runs on 55nm in early 2007. The graphics chip maker should introduce 55nm in volume production in the first quarter of 2008.

A Chinese-language Commercial Times report also cited sources at equipment makers as saying that AMD has also started pilot runs on 55nm.

Currently, the most advanced process used for production is the 65nm process. The next major advance in process technology is a shift to 45nm, which is expected to start later this year when Intel begins producing chips with that process.