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Wednesday, August 30, 2006
Toshiba Adopts Cadence Solution for 65nm Design


Cadence Design Systems announced that Toshiba has adopted Cadence QRC Extraction for its most advanced 65nm design flows.

Cadence QRC Extraction provides silicon-accurate parasitic extraction for next-generation process nodes, including sensitivity-based and chemical-mechanical polishing model-based extraction.

"To address our design and methodology requirements at 65nm and beyond, we require a solution that can deliver exceptional accuracy and includes advanced statistical and silicon variation modeling," said Takashi Yoshimori, technology executive, SoC-Design of Toshiba's semiconductor company. "After an extensive evaluation process, we found that Cadence QRC Extraction meets our requirements for 65nm accuracy today, and we have confidence that it will continue to meet our requirements for 65- and 45nm, giving us the ability to move into lower and lower geometries."

Cadence QRC Extraction provides manufacturing-aware silicon accuracy over other extraction technologies for cell-based digital designs. It dramatically reduces processing time with its near-linear performance scalability across multiple network CPUs and compute farms, said Cadence. It also delivers robust multi-corner support and native incremental signoff extraction to the Cadence Encounter digital IC platform.


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