Sunday, March 29, 2015
Search
  
Submit your own News for
inclusion in our Site.
Click here...
Breaking News
Microsoft Lists Windows 10-Compatible Phones
Intel in Talks to buy Altera: report
MediaTek Releases New High-end Smartphone Helio SoC
Google To Get Into The Operating Room
Data Requests To Microsoft Decreased
Google Defeated in English Court - Decision Opens Door for Litigation by Millions of British Apple Users
LG G4 Smartphone Coming Late April
BlackBerry Posts Quarterly Profit
Active Discussions
how to copy and move data files to dvd-rw
cdrw trouble
Need serious help!!!!
burning
nvidia 6200 review
Hello
Burning Multimedia in track 0
I'm lazy. Please help.
 Home > News > PC Parts > Toshiba...
Last 7 Days News : SU MO TU WE TH FR SA All News

Wednesday, August 30, 2006
Toshiba Adopts Cadence Solution for 65nm Design


Cadence Design Systems announced that Toshiba has adopted Cadence QRC Extraction for its most advanced 65nm design flows.

Cadence QRC Extraction provides silicon-accurate parasitic extraction for next-generation process nodes, including sensitivity-based and chemical-mechanical polishing model-based extraction.

"To address our design and methodology requirements at 65nm and beyond, we require a solution that can deliver exceptional accuracy and includes advanced statistical and silicon variation modeling," said Takashi Yoshimori, technology executive, SoC-Design of Toshiba's semiconductor company. "After an extensive evaluation process, we found that Cadence QRC Extraction meets our requirements for 65nm accuracy today, and we have confidence that it will continue to meet our requirements for 65- and 45nm, giving us the ability to move into lower and lower geometries."

Cadence QRC Extraction provides manufacturing-aware silicon accuracy over other extraction technologies for cell-based digital designs. It dramatically reduces processing time with its near-linear performance scalability across multiple network CPUs and compute farms, said Cadence. It also delivers robust multi-corner support and native incremental signoff extraction to the Cadence Encounter digital IC platform.


Previous
Next
Verbatim Launches Flash Drives with Mandatory Security Features        All News        Google CEO Joins Apple's Board
Verbatim Launches Flash Drives with Mandatory Security Features     PC Parts News      Intel Sees Quad-Cores in Q4

Source Link Get RSS feed Easy Print E-Mail this Message

Related News
Toshiba, Sandisk, Develop First 48-layer 3D NAND For SSDs
Toshiba Expands Line-up of eMMC Version 5.1 Embedded NAND Flash Memory Products
Toshiba Starts Production of 13-Megapixel CMOS Image Sensor With "Bright Mode" Video Technology
Toshiba Expands Internal and External Desktop Hard Drive Lineup With New 6TB Models
Toshiba Debuts 12.0 Gbps SAS HDD
Toshiba Starts Shipping 20-Megapixel CMOS Image Sensor For Mobile Devices
New Toshiba Smartwatch Reference Model features Bluetooth connectivity and Qi Wireless Charging
Toshiba Develops STT-MRAM Circuit For High-performance Processors
Toshiba Develops Multicore SoC For Image-Recognition Applications
Toshiba Launches 8 Megapixel CMOS Image Sensor for Smartphones and Tablets
Toshiba Introduces New APs For For IoT Solutions
Toshiba Achieves 1Tbit per Square Inch Areal Density in a 2.5-Inch Hard Disk Drive

Most Popular News
 
Home | News | All News | Reviews | Articles | Guides | Download | Expert Area | Forum | Site Info
Site best viewed at 1024x768+ - CDRINFO.COM 1998-2015 - All rights reserved -
Privacy policy - Contact Us .