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Friday, May 26, 2006
UMC, TSMC Ready for 65-nanometer X Architecture Designs


The world?s two largest contract semiconductor manufacturers have both qualified the Cadence X Architecture for their 65-nm designs.

Taiwan Semiconductor Manufacturing Company (TSMC) and UMC announced that the Cadence X Architecture has been validated for their 65-nm processes.

"TSMC and Cadence have engaged with multiple customers for 0.13-micron, 0.11-micron and 90-nm X Architecture production designs, and are now working with early customers targeting our 65-nm process. The X Architecture provides another dimension to bring cost, performance and power benefits," said Ed Wan, senior director of TSMC's design services marketing.

"UMC has been working with Cadence for several years to bring the advantages of the X Architecture to mainstream SoC designers," said Patrick T. Lin, chief SoC architect at UMC. "We are delighted to extend our readiness of this technology to the 65nm generation, as leading customers can now leverage the X Architecture with the industry's most advanced process technology to increase the competitiveness of their products."

The Cadence X Architecture is now available to customers for TSMC's 0.13-micron, 0.11-micron, 90-nm and 65-nm processes, and for UMC's 130nm, 90nm and 65nm process technologies.


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