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Tuesday, February 07, 2006
Toshiba Develops High Density FeRAM, MRAM Memory

Toshiba today announced a newly developed FeRAM?a Ferroelectric Random Access Memory?that redefines industry benchmarks for density and operating speed.

The new chip takes FeRAM storage to the 64-megabit level and pushes read and write speed to 200-megabytes a second.

In collaboration with NEC, Toshiba also said that it has developed a magnetoresistive random access memory (MRAM), which achieves a 16 Mbit density and read and write at 200-megabytes a second.

FRAM Memory

The ferroelectric memory or FeRAM has been in production now for a number of years. The products are available both as low density application specific standalone memories and as embedded memory. Applications for this low power non-volatile RAM include RFID tags and various smart cards for identification, biomedical applications and electronic money. It is also used in industrial systems, office equipment and appliances, automotive systems, consumer systems and space applications.

FeRAM combines the fast operating characteristics of DRAM and SRAM with flash memory's ability to retain data while powered off. FeRAM, like MRAM, is a low power, nonvolatile memory design that possesses an array structure allowing for the one-transitor memory cell density of standard DRAM. While MRAM derives its memory store capability from the presence of a magnetic junction tunnel, FeRAM utilizes the properties of ferroelectric capacitors to effectively detect the positioning of electrical dipoles within ferroelectric material. Unlike DRAM memories, which refresh their capacitors periodically, ferroelectric memories only refresh the arrays after a read is performed, this because the read destroys the content of the cell. If there is no read, the dipoles never flip, hence no recharge cycles are required. This allows FeRAM memory to operate at low power.

Toshiba's 64-megabit FeRAM are fabricated with 130-nanometer CMOS process technology based on Toshiba's chainFeRAM architecture, which significantly reduces memory cell size. It also integrates optimized circuitry designed to reduce the circuit area and squelch noise during read operation, and ECC, a high-speed error checking and correcting circuit that assures data reliability at high speed operation, even in severe operating conditions.

The key to the performance boost is adoption of burst mode for high-speed data transfers, according to Toshiba. Its successful integration pushes read and write speed to 200-megabytes a second?the fastest speed of any FeRAM.

Toshiba said it will continue its R&D in FeRAM, aiming for eventually use in a wide range of applications, including mobile digital equipment and computers.

MRAM Memory

The magnetoresistive random access memory (MRAM) memory is another advanced nonvolatile technology. The most important difference between the FRAM and the MRAM technologies is in maturity. FRAM has evolved from a laboratory technology to a production technology with hundreds of customers. MRAM and other advanced memory technologies hold great promise but have several major hurdles before reaching the current stage of FRAM.

Toshiba Corporation and NEC Corporation announced that they have developed an MRAM that memory that combines the highest density with the fastest read and write speed yet achieved. The new MRAM achieves a 16-megabit density and a read and write speed of 200-megabytes a second, and also secures low voltage operation of 1.8V.

The companies said that they have managed to cope with the major challenge of MRAM development to date, which is the acceleration of read speeds. The new MRAM has an improved circuit design that divides the current paths for reading and writing, realizing a faster read speed. It also reduces equivalent resistance in wiring by approximately 38% by forking the write current. These innovations together achieve a read and write speed of 200-megabytes a second and a cycle time of 34 nanoseconds. This performance is underlined by a low operating voltage of only 1.8V, the ideal voltage for mobile digital products.

Alongside advances in performance, the new MRAM achieves advances in chip size. Toshiba and NEC have introduced the above mentioned technologies and optimized overall circuit design, achieving a chip that, at 78.7mm2, is approximately 30% smaller than its equivalent without the new circuit design.

Development of these new MRAM technologies was supported by grants from Japan's New Energy and Industrial Technology Development Organization (NEDO). Full details of the new technology were presented on February 6 at ISSCC (International Solid-State Circuits Conference) 2006 in San Francisco, USA.

Basic Specifications
130-nanometer CMOS, 240-nanometer MRAM
130 nanometer CMOS
16 megabit
64 megabit
Cell size
1.872 um2
0.7191 um2
Cycle time
34 nanoseconds
60 nanoseconds
Read/Write speed (band width)
200 megabytes/second
200 megabytes/second
Power supply voltage
3.3V, 2.5V

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