Nero announced the availability of its new Nero Digital AVC/H.264 video decoder VHDL IP core
The perfect solution for ASICs and SoCs is hardware-based and capable of full ISO/IEC 14496-10 Advanced Video Coding Standard (MPEG-4 Part 10) compliance decoding up to a resolution of 4096 x 4096.
This solution has very low hardware requirements and supports Baseline, Main, Extended and High Profile. It synthesizes with major digital cell libraries, and can decode SD content with as low as 50MHz frequency, and HD 1080p and 1080i with 200MHz. It is optimized for low internal SRAM usage and provides pixel-perfect output with AVC/H.264 compliance streams and "real world" streams of different encoders from the market.
The Nero AVC decoder IP core accesses DDR or SDRAM memory over a 64-bit shared bus, making it simple to integrate with existing SoC designs. The IP core streams in source video via serial, PCI, or Ethernet, and other interface types can be implemented in a custom silicon solution along with various video controller options.
Nero is strongly supporting AVC/H.264 adoption and is therefore offering a very competitive pricing structure for this high end IP Core. Please contact email@example.com for inquiries.
Demonstrations using a board with single FPGA for HD decoding are taking place during CES 2006 at the Nero booth South Hall 1 #21568.