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Tuesday, October 18, 2005
Intel Introduces Robson Technology at IDF Taiwan


Intel gave Monday details about its next-generation dual-core mobile processor, known as Merom, and also presented its future mobile platform technology codenamed Robson, at the Intel Developer Forum (IDF) in Taiwan.

Merom is expected to succeed Yonah, Intel's first 65nm processor, which is the main part of the Napa mobile platform and is scheduled for launch in January 2006.

The Robson technology aims to extend battery life, accelerate system boot-up and provide user-visible responsiveness, said vice president of Intel's mobility group and general manager of the mobile platforms group Shmuel (Mooly) Iden. The Robson platform technology is curently under development.

Intel's new Robson cache technology ensured an almost immediate start-up of a Centrino-based notebook PC during a live demonstration at the Intel Developer Forum in here Monday.

The laptop with Robson also opened Adobe Reader in 0.4 seconds, while the other notebook required 5.4 seconds. It opened Quicken in 2.9 seconds, while the laptop without Robson technology needed 8 seconds to do the job.

The secret behind the Robson nonvolatile cache technology is NAND flash memory. Instead of booting from the hard drive, a laptop using Robson would turn to standard NAND flash memory instead. The difference saves time and battery power, according to Intel. The laptop used in the demonstration contained 128MB NAND.

Intel spoksmen did not confirm that Robson will add another deep sleep mode, with even less power consumption compared to Yonah's new enhanced deeper sleep mode, but agreed that using non-volatile memory cache potentially opens more opportunities for power saving through, for example, transferring content of CPU registers out of a processor. More technical details about Robson will be disclosed at IDF Spring.

Intel also gave details about the Merom CPU, announced by Intel in August this year at IDF Fall in San Francisco. Compared to Yonah, the 65nm CPU will have a larger level-two cache and will contain some micro-architecture innovations, according to Intel. One of these innovations will be a higher performance 4-issue out-of-order engine with deeper buffers and a pipeline extended to 14 stages. Another promised features include more power efficiency, direct L1-to-L1 cache transfer and improved memory access. Merom is also claimed to feature some substantial improvements in floating-point unit (FPU) performance.

Intel intends to launch Merom as pin-to-pin compatible with Yonah, Iden mentioned, so Napa systems are expected to be upgradeable through inserting a new processor and a BIOS upgrade.

Announced at IDF Taiwan, preliminary specifications of Yonah are following: 65nm technology, 151 million transistors (12.3 million in cores), 2MB of level-two cache shared between two cores and dynamically allocated, 667MHz front-side bus (FSB), PGA478 or BGA479 socket. In addition to dual-core Yonah and Merom, the company has already started thinking about mobile processors with four and more cores.


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