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Tuesday, October 04, 2005
TSMC Announces Production-Ready 90nm X Architecture


Taiwan Semiconductor Manufacturing Company today announced that it is ready to accept 90nm X Architecture designs.

The company has successfully qualified 90nm X Architecture design rules that can enable lower cost, higher performance and lower power designs. TSMC and Cadence Design Systems, Inc. have collaborated to validate the Cadence X Architecture design solution for the process. The two companies are now engaging mutual customers.

"In each case, we have demonstrated tangible benefits in at least one of three critical areas: cost, performance or power, depending on the design" said Ed Wan, senior director of product marketing for TSMC's design services division.

Earlier this year, ATI Technologies Cadence and TSMC successfully produced the foundry industry's first X Architecture device -- a high-performance, high-volume PCI-Express graphics processor. ATI implemented the device using the Cadence X Architecture design solution and manufactured it on TSMC's 0.11-micron process. The design eliminated one metal layer, reducing the device's die cost.

Cadence and TSMC are members of the X Initiative, a semiconductor design chain consortium chartered with accelerating fabrication of the X Architecture. The X Architecture represents a new way of orienting a chip's microscopic interconnect wires with the pervasive use of diagonal routes, in addition to traditional right-angle "Manhattan" routing. The X Architecture can provide significant improvements in chip area, performance, power consumption and cost, by enabling designs with significantly less wirelength and fewer vias (the connectors between wiring layers).


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