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Thursday, May 12, 2005
Samsung to Reduce Design Time for Nano-class ICs


Samsung Electronics Co., Ltd., has developed new diagnostic software for nano-class semiconductor products.

The new diagnostic software, ESCORT (Estimation of Chip Performance on Process Tolerance)/SRSIM (Samsung Reliability Simulator), assesses the semiconductor circuit design for potential errors in the early stages of designing nanometer-scale circuitry.

The new software can perform simulation in the preliminary design stage, detecting any potential design errors before moving on to the prototype stage. This will result in greatly reinforcing production of high-quality memory products, and reducing development time and costs.

Samsung's ESCORT software can significantly increase wafer yields through careful simulation in the early stages of the product development cycle. The Samsung SRSIM can estimate when the performance of transistors in memory chip circuits might deteriorate after a series of designated time-lapses.

The new diagnostic processes can be applied not only to memory products, but also to display drive ICs (DDI), CMOS image sensors (CIS) and system on chip (SoC) designs. By improving product yield and eliminating correction on mask, the ESCORT/SRSIM diagnostic software can shorten the product development time by at least four weeks, preventing unnecessary delays arising from a need to re-design any circuits. Based on reduced design time and increased wafer yields, the new software is projected to save as much as $30 million (U.S.) in development costs each year.


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