Panasonic announced the development of another world's smallest, the new MOS image sensor has 2.0 microm pixels..

This breakthrough allows two million pixels on a 1/4-inch sensor instead of one million. The reduction was achieved by minimizing the number of transistors. Matsushita's technological breakthrough allows two million pixels on a 1/4-inch MOS sensor instead of one million. This size reduction was also achieved without sacrificing sensitivity by minimizing the number of transistors required for each pixel. Details of the sensor will be presented at the International Solid-State Circuits Conference (ISSCC) held in San Francisco during February 6 - 10, 2005.

One problem industry has experienced with reducing pixel size in the past has been a corresponding reduction in sensitivity. Panasonic has solved the problem by developing three new technologies: the 0.15?m design rule, sharing the detection amplifier circuit, and pulse driving the electric source line.

In conventional CMOS sensors, the wiring on a chip is usually 0.25microm wide. This limits the possible miniaturization of the photodiode area. In the new sensor, the 0.15microm design rule cuts 40 per cent from the amount of space taken up by wiring, allowing more space for photodiodes.

Conventional CMOS image sensors require four transistors for each pixel: a detection amplifier circuit with three transistors, and a charge read-out transistor. In the new sensor, a detection amplifier is shared by four pixels, one each from two rows and two columns. This means that four pixels now require only one detection amplifier circuit and four charge read-out transistors (one for each pixel).

Furthermore, each detection amplifier circuit has been redesigned to need only two transistors instead of three. The detection amplifier circuit in conventional CMOS image sensors usually requires an output transistor, a resetting transistor, and a row-selecting transistor. But in the new sensor, by replacing the conventional direct electric source for pulsing, the column-selecting transistor can be eliminated. Thus the 16 transistors required by four pixels in a conventional design are reduced to just six in the new chip.